One conventional data storage system includes a storage processor, an array of magnetic disk drives and a backup power supply. The storage processor carries out a variety of data storage operations on behalf of an external host device (or simply host). In particular, the storage processor temporarily caches host data within its storage cache and, at certain times, de-stages that cached data onto the array of magnetic disk drives. If the data storage system is set up so that it acknowledges write requests from the host once the data reaches the storage cache rather than once the data reaches the array of magnetic disk drives, the host will enjoy shorter transaction latency.
In a typical computing system including a typical data storage system, different types of serious failures may occur, such as power failures, software crashes, or critical hardware failures in components such as disk drives, a fan, a power supply, a central processing unit (CPU) or memory boards, or an I/O bus.
Some data storage systems employ backup power supplies to prevent the loss of data from the storage caches in the event of power failures. For example, suppose that such a data storage system loses its steady state source of electrical power (e.g., power from the street) during operation. In such a situation, a set of backup power supplies provides reserve power to the storage processor and to a persistent storage device (e.g., the array of magnetic disk drives) for a short period of time (e.g., 30 seconds). During this time, the storage processor writes the data from its storage cache onto the persistent storage device so that any data which has not yet been properly de-staged is not lost. Once power from the main power feed returns, the storage processor loads the data from the persistent storage device back into the storage cache. At this point, the data storage system is capable of continuing normal operation.
Typically in a computing system a non-maskable interrupt (NMI) or system management interrupt (SMI) can be generated to handle a serious failure. When an SMI or NMI is asserted, the CPU is aware that a catastrophic failure has occurred which necessitates the shut-down of the system. Other types of failures such as an address parity error may cause the NMI to be asserted to the CPU.
When the CPU receives the SMI signal, the CPU operation mode shifts to a system management mode (to be referred to as an SMM hereinafter) to start an interrupt control process stored in the system's BIOS-ROM. The interrupt control process executes an interrupt control process corresponding to the interrupt signal requested from the CPU.
In a CPU available from Intel Corp., U.S.A., the SMM means a CPU operation mode set in shift of the CPU to the interrupt control process in the BIOS-ROM when an SMI# signal is input from the computer system to the CPU.
While the CPU is in the SMM, no computer system can request a new interrupt (e.g., IRQ, INTR, or SMI) from the CPU. The interrupt control process must directly execute a series of processes.